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preliminary data this is preliminary information on a new product now in deve lopment or undergoing evaluation. details are subject to change without notice. december 2010 doc id 17116 rev 3 1/42 42 L3G4200D mems motion sensor: ultra-stable three-axis digital output gyroscope features three selectable full scales (250/500/2000 dps) i 2 c/spi digital output interface 16 bit-rate value data output 8-bit temperature data output two digital output lines (interrupt and data ready) integrated low- and high-pass filters with user- selectable bandwidth ultra-stable over temperature and time wide supply voltage: 2.4 v to 3.6 v low voltage-compatible ios (1.8 v) embedded power-down and sleep mode embedded temperature sensor embedded fifo high shock survivability extended operating temperature range (-40 c to +85 c) ecopack ? rohs and ?green? compliant applications gaming and virtual reality input devices motion control with mmi (man-machine interface) gps navigation systems appliances and robotics description the L3G4200D is a low-power three-axis angular rate sensor able to provide unprecedented stablility of zero rate level and sensitivity over temperature and time. it includes a sensing element and an ic interface capable of providing the measured angular rate to the external world through a digital interface (i 2 c/spi). the sensing element is manufactured using a dedicated micro-machining process developed by stmicroelectronics to produce inertial sensors and actuators on silicon wafers. the ic interface is manufactured using a cmos process that allows a high level of integration to design a dedicated circuit which is trimmed to better match the sensing element characteristics. the L3G4200D has a full scale of 250/500/ 2000 dps and is capable of measuring rates with a user-selectable bandwidth. the L3G4200D is available in a plastic land grid array (lga) package and can operate within a temperature range of -40 c to +85 c. lga-16 (4x4x1.1 mm) table 1. device summary order code temperature range (c) package packing L3G4200D -40 to +85 lga-16 (4x4x1.1 mm) tray L3G4200Dtr -40 to +85 lga-16 (4x4x1.1 mm) tape and reel www.st.com
L3G4200D 2/42 doc id 17116 rev 3 contents 1 block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 mechanical and electrical characte ristics . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.4 communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4.1 spi - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4.2 i2c - inter ic control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.5 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.6 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.6.1 sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.6.2 zero-rate level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.6.3 self-test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.7 soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3 main digital blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2 fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2.1 bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2.2 fifo mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2.3 stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2.4 bypass-to-stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2.5 stream-to-fifo mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2.6 retrieve data from fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4 application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5 digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1 i2c serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1.1 i2c operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.2 spi bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2.1 spi read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 L3G4200D doc id 17116 rev 3 3/42 5.2.2 spi write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.2.3 spi read in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6 output register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.1 who_am_i (0fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.2 ctrl_reg1 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.3 ctrl_reg2 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.4 ctrl_reg3 (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.5 ctrl_reg4 (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.6 ctrl_reg5 (24h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.7 reference/datacapture (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.8 out_temp (26h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.9 status_reg (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.10 out_x_l (28h), out_x_h (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.11 out_y_l (2ah), out_y_h (2bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.12 out_z_l (2ch), out_z_h (2dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.13 fifo_ctrl_reg (2eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.14 fifo_src_reg (2fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.15 int1_cfg (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.16 int1_src (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.17 int1_ths_xh (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.18 int1_ths_xl (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.19 int1_ths_yh (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.20 int1_ths_yl (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.21 int1_ths_zh (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.22 int1_ths_zl (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.23 int1_duration (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 list of tables L3G4200D 4/42 doc id 17116 rev 3 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 3. filter values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 4. mechanical characteristics @ vdd = 3.0 v, t = 25 c, unless otherwise noted . . . . . . . . . . . . 10 table 5. electrical characteristics @ vdd =3.0 v, t=25 c, unless otherwise noted . . . . . . . . . . . . . . . . 11 table 6. temp. sensor characteristics @ vdd =3.0 v, t=25 c, unless otherwise noted . . . . . . . . . . . 11 table 7. spi slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 8. i2c slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 9. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 10. pll low-pass filter component values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0 table 11. serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 12. i2c terminology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 13. sad+read/write patterns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 14. transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 15. transfer when master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 16. transfer when master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 23 table 17. transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 23 table 18. register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 19. who_am_i register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 20. ctrl_reg1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 21. ctrl_reg1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 22. dr and bw configuration setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 23. power mode selection configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 24. ctrl_reg2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 25. ctrl_reg2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 26. high pass filter mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 27. high pass filter cut off frecuency configuration [hz] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 28. ctrl_reg1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 29. ctrl_reg3 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 30. ctrl_reg4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 31. ctrl_reg4 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 32. self test mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 33. ctrl_reg5 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 34. ctrl_reg5 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 35. out_sel configuration setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 36. int_sel configuration setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 37. reference register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 38. reference register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 table 39. out_temp register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 40. out_temp register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 41. status_reg register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 42. status_reg description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 43. reference register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 44. reference register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 table 45. fifo mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 46. fifo_src register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 47. fifo_src register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 48. int1_cfg register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 L3G4200D list of tables doc id 17116 rev 3 5/42 table 49. int1_cfg description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 50. int1_src register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 51. int1_src description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 52. int1_ths_xh register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 53. int1_ths_xh description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 54. int1_ths_xl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 55. int1_ths_xl description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 56. int1_ths_yh register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 57. int1_ths_yh description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 58. int1_ths_yl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 59. int1_ths_yl description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 60. int1_ths_zh register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 61. int1_ths_zh description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 62. int1_ths_zl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 63. int1_ths_zl description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 64. int1_duration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 65. int1_duration description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 66. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 list of figures L3G4200D 6/42 doc id 17116 rev 3 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2. pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. L3G4200D external low-pass filter values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. spi slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 5. i2c slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 6. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 7. bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 8. fifo mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 9. stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 10. bypass-to-stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 11. trigger stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 12. L3G4200D electrical connections and external component values . . . . . . . . . . . . . . . . . . 20 figure 13. read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 14. spi read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 15. multiple byte spi read protocol (2-byte example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 16. spi write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 17. multiple byte spi write protocol (2-byte example). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 18. spi read protocol in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 19. int1_sel and out_sel configuration block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 20. wait disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 21. wait enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 22. lga-16: mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 L3G4200D block diagram and pin description doc id 17116 rev 3 7/42 1 block diagram and pin description figure 1. block diagram the vibration of the structure is maintained by drive circuitry in a feedback loop. the sensing signal is filtered and appears as a digital signal at the output. 1.1 pin description figure 2. pin connection fifo trimming circuit s reference mixer charge amp clock low-pa ss filter + x,y,z i2c s pi c s s cl/ s pc s da/ s do/ s di s do y+ z+ y- z- x+ x- driving ma ss feed ba ck loop m u x a d d c i g i t a l f i l t e r i n g control logic & interrupt gen. int1 drdy/int2 a d c t e m p e r a t u r e s e n s o r 1 2 & pha s e generator ? am07225v1 (top view) direction s of the detectable angular rate s 1 x vdd_io s cl/ s pc s da/ s di/ s do s do/ s a0 re s re s re s re s int drdy/int2 c s re s pllfilt re s vdd gnd 1 8 12 5 4 9 1 3 16 +? z +? x bottom view +? y am07226v1 block diagram and pin description L3G4200D 8/42 doc id 17116 rev 3 figure 3. L3G4200D external low-pass filter values (a) table 2. pin description pin# name function 1 vdd_io power supply for i/o pins 2 scl spc i 2 c serial clock (scl) spi serial port clock (spc) 3 sda sdi sdo i 2 c serial data (sda) spi serial data input (sdi) 3-wire interface serial data output (sdo) 4 sdo sa0 spi serial data output (sdo) i 2 c least significant bit of the device address (sa0) 5cs spi enable i 2 c/spi mode selection (1:spi idle mode / i 2 c communication enabled; 0: spi communication mode / i 2 c disabled) 6 drdy/int2 data ready/fifo interrupt 7 int1 programmable interrupt 8 reserved connect to gnd 9 reserved connect to gnd 10 reserved connect to gnd 11 reserved connect to gnd 12 reserved connect to gnd 13 gnd 0 v supply 14 pllfilt phase-locked loop filter (see figure 3 ) 15 reserved connect to vdd 16 vdd power supply a. pin 14 pllfilt maximum voltage level is equal to vdd. % 4 % % c r c e k v q t h q t v q r k p ) 0 & . q y r c u u h k n v g t # / x L3G4200D block diagram and pin description doc id 17116 rev 3 9/42 table 3. filter values parameter typical value c1 10 nf c2 470 nf r2 10 k ? mechanical and electrical characteristics L3G4200D 10/42 doc id 17116 rev 3 2 mechanical and electrical characteristics 2.1 mechanical characteristics table 4. mechanical characteristics @ vdd = 3.0 v, t = 25 c, unless otherwise noted (1) symbol parameter test condition min. typ. (2) max. unit fs measurement range user-selectable 250 dps 500 2000 so sensitivity fs = 250 dps 8.75 mdps/digit fs = 500 dps 17.50 fs = 2000 dps 70 sodr sensitivity change vs. temperature from -40 c to +85 c 2 % dvoff digital zero-rate level fs = 250 dps 10 dps fs = 500 dps 15 fs = 2000 dps 75 offdr zero-rate level change vs. temperature (3) fs = 250 dps 0.03 dps/c fs = 2000 dps 0.04 dps/c nl non linearity (4) best fit straight line 0.2 % fs dst self-test output change fs = 250 dps 130 dps fs = 500 dps 200 fs = 2000 dps 530 rn rate noise density bw = 50 hz 0.03 dps/ sqrt(hz) odr digital output data rate 100/200/ 400/800 hz top operating temperature range -40 +85 c 1. the product is factory calibrated at 3.0 v. the operational power supply range is specified in table 5 . 2. typical specificat ions are not guaranteed. 3. min/max values have been estimated based on the m easurements of the current gyros in production. 4. guaranteed by design. L3G4200D mechanical and electrical characteristics doc id 17116 rev 3 11/42 2.2 electrical characteristics 2.3 temperature sensor characteristics table 5. electrical characteristics @ vdd =3.0 v, t=25 c, unless otherwise noted (1) symbol parameter test condition min. typ. (2) max. unit vdd supply voltage 2.4 3.0 3.6 v vdd_io i/o pins supply voltage (3) 1.71 vdd+0.1 v idd supply current 6.1 ma iddsl supply current in sleep mode (4) selectable by digital interface 1.5 ma iddpdn supply current in power-down mode selectable by digital interface 5a to p operating temperature range -40 +85 c 1. the product is factory calibrated at 3.0 v. 2. typical specificat ions are not guaranteed. 3. it is possible to remove vdd maintaining vdd_io withou t blocking the communication busse s, in this condition the measurement chain is powered off. 4. sleep mode introduces a faster turn -on time compared to power-down mode. table 6. temp. sensor characteristics @ vdd =3.0 v, t=25 c, unless otherwise noted (1) symbol parameter test condition min. typ. (2) max. unit tsdr temperature sensor output change vs. temperature -1 c/digit todr temperature refresh rate 1 hz to p operating temperature range -40 +85 c 1. the product is factory calibrated at 3.0 v. 2. typical specificat ions are not guaranteed. mechanical and electrical characteristics L3G4200D 12/42 doc id 17116 rev 3 2.4 communication interface characteristics 2.4.1 spi - serial peripheral interface subject to general operating conditions for vdd and top. figure 4. spi slave timing diagram (b) table 7. spi slave timing values symbol parameter value (1) unit min. max. tc(spc) spi clock cycle 100 ns fc(spc) spi clock frequency 10 mhz tsu(cs) cs setup time 5 ns th(cs) cs hold time 8 tsu(si) sdi input setup time 5 th(si) sdi input hold time 15 tv(so) sdo valid output time 50 th(so) sdo output hold time 6 tdis(so) sdo output disable time 50 1. values are guaranteed at 10 mhz clock fr equency for spi with both 4 and 3 wires, based on characterization results; not tested in production. b. measurement points are done at 0.2vdd_io and 0.8vdd_io, for both input and output ports. 6 3 & |